Semiconductor chip assemblies must fit into increasingly smaller spaces as electronic device sizes become smaller. For example, in mobile phones or table computers, there is very little space to arrange components inside devices that may be less than one half an inch thick. Yet technical challenges such as heat dissipation must be dealt with in the confines of ever decreasing physical space. Additionally, pressure to reduce cost is ever present.
Configurations for semiconductor chip assemblies are desired that effectively utilize limited space within an electronic device, with acceptable or improved performance.